Increasingly higher resolution Digital-to-Analogue Converters (DAC) are being developed and implemented in instrumentation and consumer electronics. The number of bits presents an overall indication of the devices' precision, the theoretically achievable resolution however is never reached due to non-linear behaviour specific for each device/production series, set aside aging and other physical influences. Therefore, the transfer function of a digital-to-analogue converter (DAC) is always an approximation of the ideal theoretical curve.
Several parameters are used to describe the quality of a DAC such as resolution, monotonicity, differential & integral linearity. The most severe parameter is the integral linearity. The error function associated with the deviation of the actual values from the ideal transfer curve is called the integral non-linearity. This is nothing else than the difference between the theoretical and measured DAC transfer function over the entire operating range the device can cover. It is common to see that DAC chips with a 20 . . . 24 bit resolution typically have an integral linearity of 16 bit at its best.
In order to improve this, a first step consists in determining the deviation of the ideal behaviour. This can be obtained by measuring all possible DAC output values. However, this would be a time consuming procedure since a 24 bit device has a total of over 16 million input codes! Also, due to the very high resolution of a 24-bit DAC, the voltages need to be measured with extremely high precision (typically using a 8.5 digit multimeter), which implies that a single measurement will take about one second to achieve the required precision.
Patent document DE 4003682 discloses a D/A converting system wherein, during an intermediate matching operation, the output signals are sequentially measured at high velocity. The detected defects are then digitised and stored in a memory. The memory address signal is formed by the coarse positions of each digital signal at the input of D/A converter circuit consisting of a coarse converter and a fine converter. During normal operation, the memory output signal is fed to a third (correction) D/A converter, the weighted output signal of which is added to the output signal of said D/A converter circuit. The corrections have the size of only half a LSB.
The D/A converting system in DE 4003682 needs 3 D/A converters. The proposed solutions make use of a set of low resolution DACs arranged in such a way as to obtain a higher resolution. However, the integral linearity of this configuration cannot be guaranteed, resulting in unwanted distortion. Also restrictions, regarding linearity, are implied with respect to the set of DACs.
A very similar approach can be found in U.S. Pat. No. 4,843,392.